• The details of an Arm Cortex-A35/53/57/72 processor core
• The details of the cache coherency logic
• Memory management for Arm v8-A based devices
• Assembly programming for the A64 instruction set
• Writing efficient C code for the Cortex-A35/53/57/72
• Bringing up an Arm Cortex-A35/53/57/72 bare metal system

Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required. C programming for Embedded Systems training is also available from Bicard.

A carefully crafted combination of content from Arm and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.

Training material includes fully indexed course notes creating a complete reference manual.

Architecture Overview

Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model

Software Engineer's Cortex-A35/53/57/72

Core pipelines • Configuration options • Branch prediction • Cache overview • Data cache coherency • Memory management • Micro-architectural features • Interrupts and bus interfaces • Debug and timers • Big-little

A64 ISA Overview

Registers • Loads and stores • Data processing and control flow • Scalar floating-point and SIMD

Synchronization

Synchronization in ARMv8-A • Local and Global Exclusive Monitors

AArch64 Exception Model

The AArch64 exception model • Interrupts • Synchronous exceptions • SError • exceptions • Exceptions in EL2 and EL3

Booting

Booting an ARMv8-A processor in AArch64 • Booting multi-core and multi-processor systems • Real-world booting

Caches and Branch Prediction

General Cache Information • Cache Attributes • Cache Maintenance Operations • Cache Discovery

Memory Management

Memory Management theory • Stage 1 Translations at EL1/0 • Translations at EL2 / EL3 • TLB maintenance

Memory Model

Types • Attributes • Alignment and endianness • Tagged pointers

Barriers

Data barriers • Instruction barriers

ARMv8-A OS Support Features

Context Switching • Modifying Translation Tables • Privilege Escalation Protections • Timers

Secure Environments

Why do we need a Secure environment? • Software stack • System architecture

Cache Coherency

Introduction to coherency • Coherency details - multi-core processors • Coherency details - multi-processor systems

Virtualization

What is virtualization? • ARM virtualization support • Memory management • Exception handling

Cortex-A Power Management

ARM core power modes • Power control • ARM multi-core processor power modes • Power state coordination

Embedded Software Development

Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations

GNU Compiler Hints and Tips

Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues

GNU Linker Hints and Tips

Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries

ARMv8-A Debug

Introduction to Debug • Types of Debug • Debug Facilities • External Debug • Self-hosted Debug • CoreSight • Debug Features • Trace

NEON Benchmarking and Performance Analysis

Introduction • Performance Monitoring Hardware: PMU • Cycle Accurate Trace: Trace • Macrocells • Streamline Performance Analysis

Appendix Software Engineer's Guide to System Fabric

Interrupt Controller • System MMU • TrustZone Address Space Controller • Generic Timer

The learning is reinforced with unique Lab Exercises using an Armv8-A 64 bit instruction set simulator and covering assembly programming, exception handling and setting up the caches and MMU.

• Lab exercises for assembly programming cover the concepts of data processing, flow control, and rely on the GNU development tool-set.
• Exception handling lab exercises look at setting up various exception levels vector table and execution modes as well as executing hypervisor and secure calls.
• The Memory management lab takes you though the steps involved in implementing a typical system memory configuration using the MMU.
• The performance monitoring unit lab takes you through the steps required to configure and enable performance monitoring inside your processor.